The present invention relates to a graphics controller for high speed transmission of memory read commands. More particularly, the present invention is directed to a graphics controller with a read/write state machine for accepting high speed transmission of memory read commands initiated by the CPU.
A common practice in the art of computer architecture is to move frequently performed, computationally intensive operations from the CPU to a special purpose functional unit, such as a graphics controller. The graphics controller is typically a separate integrated circuit (xe2x80x9cchipxe2x80x9d). In a computer system with a graphics controller chip, the graphics controller handles various tasks associated with displaying images on a display (such as converting primitive data to pixels), freeing the CPU to perform other tasks. Moving graphics operations from the CPU to the graphics controller improves the performance of the computer system. In practice, however, the amount of improvement is generally not as great as expected. The reason is that the transfer of data between the CPU and the graphics controller becomes a bottleneck that places a limit on the amount of improvement that can be realized. To illustrate the effect of the data transfer bottleneck, consider that in a typical computer system the CPU theoretically requires only 2 bus clock cycles (xe2x80x9cBCLKsxe2x80x9d) to perform a memory write command and 4 BCLKs to perform a memory read command. In practice, however, writing to a prior art graphics controller requires 5 BCLKs and reading requires up to 8 BCLKs. During the 3-4 additional BCLKs that are required with a prior art graphics controller, the CPU does not perform any useful work.
The transfer of data between a CPU and a graphics controller involves a number of steps. These steps must be coordinated so that data is not transferred to the graphics controller faster than it can accept it and so that the CPU knows when the data it has requested is available. To regulate the flow of data from the CPU to the graphics controller, the graphics controller includes a read/write control circuit that can be defined as a read/write state machine.
The read/write state machine typically has four states: An xe2x80x9cidlexe2x80x9d state in which the graphics controller waits for a command from the CPU; a xe2x80x9cpausexe2x80x9d state in which the read/write state machine checks whether the graphics controller is ready to process the command; a xe2x80x9crequestxe2x80x9d state in which the graphics controller begins processing the command; and, an xe2x80x9cendxe2x80x9d state in which the graphics controller finishes processing the command. The read/write state machine transitions from state to state in a fixed sequence for each memory cycle. When the read/write state machine receives a command, it transitions sequentially from the idle state to the pause state to the request state to the end state. From the end state, the read/write state machine returns to the idle state where it waits for the next command. While the read/write state machine may remain in a state for one clock period or longer, depending on the type and sequence of commands, the state transition sequence does not change.
A bottleneck occurs, for example, when the CPU issues a memory read command. The graphics controller requires more time to process the memory read command than the CPU requires to send a subsequent command. Because the CPU does not perform any useful work while it is waiting for the graphics controller to accept another command, the prior art read/write state machine degrades the overall performance of the computer system.
Accordingly, there is a need for a graphics controller that is capable of accepting high speed transmission of memory read commands initiated by a CPU.
The invention disclosed herein is a graphics controller for high speed transmission for memory read commands. Within the scope of the invention, there is a graphics controller chip for use with an off-chip CPU issuing a plurality of commands. The graphics controller chip preferably comprises a logic circuit coupled to a first memory. The logic circuit is adapted to respond to a first issued command from a CPU by determining whether the condition that a first command is a memory read command is true. If the condition is true, the logic circuit causes the graphics controller chip to store the first command in the first memory and to begin carrying out the first command. If the condition is false, the logic circuit causes the graphics controller chip to check whether the graphics controller chip is ready to carry out the first command. If the graphics controller chip is not ready to carry out the first command, the logic circuit causes the graphics controller chip to continue checking and to send a signal to the CPU indicating that the graphics controller chip is ready to receive a second command from the CPU.
The foregoing and other objectives, features, and advantages of the invention will be more readily understood upon consideration of the following detailed description of the invention, taken in conjunction with the accompanying drawings.